IEEE Std 802.3cb-2018 pdf download – IEEE Standard for I Ethernet Amendment 1: Physical Layer Specifications and Management Parameters for 2.5 Gb/s and 5 Gb/s Operation over Backplane.
45.2.3.15.4 BASE-R and MultiGBASE-T PCS high BER (3.32.1) Change the last sentence of the first paragraph of 45.2.3.15.4 as shown: This bit is a direct reflection of the state of the hi ber variable in the BER monitor state diagrams as defined in 49.2.13.2.2 for 5/10/25GBASE-R and in 82.2.19.2.2 for 40/100GBASE-R. 45.2.3.15.5 BASE-R and MultiGBASE-T PCS block lock (3.32.0) Change the third sentence of 45.23.15.5 as shown: For a 10GBASE R or 5/10/25GBASE-R PCS, this bit is a direct reflection of the state of the block_ lock variable defined in 49.2.13.2.2. 45.2.3.16 BASE-R and MultiGBASE-T PCS status 2 register (Register 3.33) 45.2.3.16.1 Latched block lock (3.33.15) Change 45.2.3.16.1 as shown: When read as a one, bit 3.33.15 indicates that the 5/10/25/40/100GBASE-R or a member of the MultiGBASE-T set PCS has achieved block lock. When read as a zero, bit 3.33.15 indicates that the 5/10/25/40/100GBASE-R or a member of the MultiGBASE-T set PCS has lost block lock. The latched block lock bit shall be implemented with latching low behavior. This bit is a latching low version of the 5/10/25/40/100GBASE-R and MultiGBASE-T PCS block lock status bit (3.32.0).
45.2.3.16.4 Errored blocks (3.33.7:0) Change the first sentence of 45.23.16.4 as shown: The errored blocks counter is an eight-bit count defined by the counter errored_ block_ count specified in 49.2.14.2 for 5/10/25GBASE-R， in 82.3.1 for 40/100GBASE-R, in 126.3.7.2 for 2.5GBASE-T and 5GBASE-T, in 55.3.7.2 for 10GBASE-T, and in 113.3.7.2 for 25GBASE-T and 40GBASE-T. Change the title and the first and second sentences of 45.2.3.17 as shown: 45.2.3.17 5/10/25GBASE-R PCS test pattern seed A (Registers 3.34 through 3.37) The assignment of bits in the 5/10/25GBASE-R PCS test pattern seed A registers is shown in Table 45- -189. This register is only required when the 5GBASE-R.10GBASE-R. or 25GBASE-R capability is supported. Change the title of Table 45- 189 as shown: Table 45- 189- 5/10/25GBASE-R PCS test pattern seed A 0-3 register bit definitions Change the title and the first and second sentences of 45.2.3.18 as shown: 45.2.3.18 5/10/25GBASE-R PCS test pattern seed B (Registers 3.38 through 3.41) The assignment of bits in the 5/10/25GBASE-R PCS test pattern seed B registers is shown in Table 45- 190. This register is only required when the 5GBASE-R, 10GBASE-R, or 25GBASE-R capability is supported.