IEEE Std 1801a-2014 pdf download – IEEE Standard for Design and Verification of Low-Power Integrated Circuits—Amendment 1

02-25-2022 comment

IEEE Std 1801a-2014 pdf download – IEEE Standard for Design and Verification of Low-Power Integrated Circuits—Amendment 1.
5.4 Boolean expressions Insert the following paragraph immediately after the third paragraph, which begins “A Boolean expression may also contain…”: In certain commands, logic values X, 0, 1, Z can be specified. These represent values of a predefined logic type in the relevant hardware description language. For VHDL, the predefined logic type is type ieee.std_logic_1164.std_ulogic, or any subtype thereof. For SystemVerilog, the predefined logic type is type Logic. 5.6 Attributes of objects Delete the first paragraph and insert new paragraphs as follows: HDLs include a mechanism for specifying properties of objects. These properties are called attributes. Certain UPF properties can be annotated directly in HDL source descriptions using attributes. The semantic for properties specified using HDL attributes is the same as the corresponding behavior defined by the UPF command alternative (see Clause 6). Table 4 enumerates the HDL attributes defined for UPF-compliant implementations. UPF supports the specification of attributes, or properties, of objects in a design. These attributes provide information that supports or affects the meaning of related UPF commands. Such attributes can also be defined with HDL attribute specifications in design code or with Liberty attribute specifications in a Liberty model. Table 4 enumerates the attributes that have a predefined meaning in UPF and for each attribute, the UPF command that can be used to define that attribute.
The HDL attributes in Table 4 all take values that are string literals. Where a list of names is required, the names in the list should be separated by spaces and without enclosing braces ({}). These attributes can also be specified using the attribute mechanism in SystemVerilog code or using attribute specifications in VHDL code. To attach a UPF attribute to an object in a VHDL context, the UPF attribute shall be declared first, with a data type of STD. Standard. String (or the equivalent), before any attribute specification for that attribute. For determination of precedence (see 5.8), attributes specified in HDL code are treated as if they were implicitly specified using the UPF command set_port_attributes -model -ports (for port attributes) or the UPF command set_design_attributes -models (for design attributes).

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