IEC 60749-41:2020 pdf download – Semiconductor devices – Mechanical and climatic test methods – Part 41: Standard reliability testing methods of non-volatile memory device

03-05-2022 comment

IEC 60749-41 :2020 pdf download – Semiconductor devices – Mechanical and climatic test methods – Part 41: Standard reliability testing methods of non-volatile memory device. Data patterns during cycling The data pattern used for endurance cycling shall be agreed upon between supplier and user, and the rationale documented. It is important to cycle enough sectors of blocks during the cycling period taking into account for the target application models. See Note 1 to Entry 3.4 for a discussion of the trade-offs involved in the selection of data pattern for cycling. The purpose of many qualifications is to test the device for the broadest possible range of failure mechanisms. The broadest possible range of failure mechanisms can be detected when the data pattern includes the full range of logic levels and adjacency conditions that would occur in actual use. For example, this full range can be achieved if the following three conditions are met. First, the data in the memory cells is cycled between all available logic states in equal measure. For example, in an SBC memory half the cells would be programmed and half left erased in any one cycle, whereas in a 4-level cell memory one-quarter of the cells would be written to each of the four available levels in any given cycle. Second, the positions of 1 s and 0s are non-uniform, ideally quasi-random, so that all possible adjacency configurations are represented. For example, a data pattern consisting of a mix of bytes with data patterns 00H (zero zero hexadecimal), 55H, AAH, 33H, CCH, and FFH would create a wide range of adjacency patterns. Third, the data pattern in successive cycles is not the same, but rather follows a sequence. Best practice is to ensure, in this sequence, that some cells are written to all available logic states while other cells are re-written to the same logic state in every cycle. For example, in an SBC memory, a byte that was cycled to AAH in even- numbered cycles and 5AH in odd-numbered cycles would have four cells that would be written to 0s and 1 s in alternating cycles, two cells that are re-written to 0 in every cycle, and two cells that are re-written to 1 in every cycle. Intentional delays between cycles The degradation rate of EEPROM products can depend strongly on the cycling frequency. That is because some cycling-induced damage mechanisms exhibit partial recovery in between cycles; increasing the cycling rate can prevent that recovery and lead to early failures. Typical recoverable degradation mechanisms are the detrapping of charge trapped during cycling in the transfer-dielectric layer of floating gate devices, or detrapping of excess trapped charge in trapping-based non-volatile memories. Under user-mode application the product cycle count is spread over few years and the excess trapped charge can detrap between cycles, but if the product is run to maximum cycle count in few hours or days under qualification test mode, excess trapped charge will accumulate, leading to early product failure during the endurance cycling itself or in the following data retention test. To avoid unrealistic cycling during qualification testing the qualification flow can specify intentional delays to be added between cycles. This describes methods for inserting relaxation delays during cycling and the rules and limitations that apply. The methods comprise: i) Cycling at elevated temperature (relaxation delays distributed evenly between cycles); ii) Cycling at elevated temperature at reduced cycle frequency (delays entered between each two cycles and / or between groups of cycles); iii) Ambient temperature cycling with high-temperature bake intervals inserted between groups of cycles. The rule governing the insertion of cycling delays is that the resultant relaxation due to insertion of bake delays should not exceed the matching relaxation under user mode conditions. The total duration of inserted delays should be calculated from the difference between the intended use temperature and the delay temperatures, using the activation energy of the recovery mechanism. Combination of the above methods is allowed as long as the combination obeys this rule.

Download infomation Go to download
Note: If you can share this website on your Facebook,Twitter or others,I will share more.


Anonymous netizen Fill in information